Intel has used a model it called “tick/tock” for about a decade now and that model has gone off without a hitch, but new challenges would indicate that model is changing.

It used to be that Intel would introduce a new microarchitecture and die shrink at the same time. As chips became more complex, and die shrinks more challenging, Intel slowed things down. A “tick” would be a die shrink of an existing microarchitecture while a “tock” would be a new microarchitecture with the old manufacturing process.

For years, this worked smoothly. Now comes word that Intel is struggling to get down to 10nm, just as it struggled to get down to 14nm. We’re talking about transistor gates where the thickness is measured in atoms. So it’s no easy task.

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