The concept of 3D memory stacking has been all talk and no silicon, but the silicon is getting much closer. Both Toshiba and the Micron/Intel alliance are preparing to sample densely-stacked 3D memory chips in the next 12 months.

3D stacking means just that. Traditionally, silicon chips are one plane; everything is flat, a 2D design. If you want to make a denser chip, you have to make it bigger because everything needs to be spread out. In a 3D memory design, the cells and interconnects are stacked up like Legos.

What’s really nice about 3D stacking is that the memory makers don’t need to go to bleeding edge process technology. Instead of shrinking size of each cell to make it thinner, 3D lets the manufacturers pile more memory on in the same physical space. It may be 48 layers but when you are at 20 nanometers, it’s not like your memory chips will look like a Xeon processor. 3D means stacking up, not out, so you have the same chip size, just a slight thicker.

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